As Moore’s Law gradually becomes ineffective, the semiconductor industry seeks new paths to performance growth. At the 2026 IEEE ISCAS conference in Shanghai, Huawei said it has shifted performance optimization from “geometric size” to “time compression,” and validated this through engineering practice (using 381 chips designed and mass-produced over the past six years).
In her keynote speech at ISCAS 2026, He Tingbo, president of Huawei Semiconductor, began by saying, “Over the past six years, I’ve often been asked: How did you survive and return to the forefront in highly competitive industries such as smartphones and AI?”
He continued, “Six years ago, geometric miniaturization reached a plateau. We began to rethink Moore’s Law and the nature of electronic systems. We quickly realized that the evolution of semiconductors wasn’t just about geometric miniaturization. In fact, geometric miniaturization also brought benefits in the time dimension. For example, faster transistors, faster circuit response speeds, higher chip frequencies, and so on.”
Huawei has since shifted its focus from geometric miniaturization to time-scale miniaturization—the τ law—taking time miniaturization as a new guiding principle for the evolution of electronic systems.
Huawei’s τ Law
τ scaling expressed as “Her’s Law” (Source: Huawei)
An interesting detail is that the τ law is also often called Her’s Law. He Tingbo first proposed this law, and internally at Huawei, it’s commonly referred to as He’s Law, a name that perfectly matches the pronunciation of Her’s Law.
The shift from geometric scaling to temporal scaling
Huawei’s τ Law
The shift from geometric scaling to temporal scaling (Source: Huawei)
The τ law stems from a renewed understanding of the essence of Moore’s Law. He pointed out: “Geometric scaling not only brings changes in size but also benefits the time dimension, such as faster transistor switching speeds, shorter circuit response times, and higher chip frequencies. From this perspective, space and time are ‘two sides of the same coin’; even if geometric scaling slows down, time-level optimization can continue.”
Therefore, the question is not ‘Can transistors continue to shrink?’ but ‘Can systems time continue to shorten?’ In engineering, this abstract concept is further solidified: τ can essentially be mapped to RC delay (τ ≈ RC, R is resistance, C is capacitance).
In practical implementation, Huawei proposes a multi-level ‘folding’ design method.
Huawei president He Tingbo presents τ scaling at ISCAS in Shanghai
Huawei president He Tingbo presents τ scaling at ISCAS in Shanghai. (Source: Huawei)
Folding: Shortening the path through structural reconstruction
The basic idea of folding, upon which τ scaling relies at the implementation level, is to directly shorten the signal propagation distance through three-dimensional structural rearrangement, thereby reducing RC delay.
Huawei claims its LogicFolding architecture reduces path length and RC delay by distributing critical path logic across vertical active layers and utilizing hybrid bonding. Traditional circuit delay can be expressed as τ ∝ path length × RC—folding directly reduces path length through spatial reconfiguration. System performance is ultimately limited by the propagation delay between flip-flops on the critical path, which is primarily determined by logic depth and interconnect RC.
“Therefore, the core of optimization is not simply increasing the number of transistors, but compressing the critical path,” He explained. “In this context, LogicFolding significantly shortens signal propagation paths and reduces parasitic resistance and capacitance by redistributing combinational logic on the critical path across different physical planes, thereby compressing propagation time. Simultaneously, the cross-layer layout also makes clock distribution more concentrated, significantly reducing clock skew and further compressing timing margins, ultimately leading to higher operating frequencies.”
He continued, “This approach relies on clearly defined process boundary conditions. After multiple rounds of exploration, Huawei pointed out that the hybrid bonding pitch must be controlled within three times the top metal pitch. At the current top metal pitch of approximately 720 nm, this means the bonding pitch must be less than 2 μm. When this condition is met, cross-layer connections can be equivalent to an additional metal layer, transforming LogicFolding from theory to engineering feasibility. It is precisely at this critical point that its so-called ‘performance leap’ is realized.”
Based on this design methodology, Huawei achieved its first mass-production verification in its latest generation Kirin chip.
The Kirin 2026 adopts the ‘free logic design’ concept, extending the processing core from a traditional single-layer structure to a two-layer active architecture, enabling LogicFolding to enter chip-level applications.
Kirin 2026 smartphone SoC will be the first to use LogicFolding. (Source: Huawei)
The results show that the Kirin 2026 SoC delivers a “step-like” improvement: In the previous three years, transistor density only increased from 126 MTr/mm² to 155 MTr/mm², but after introducing LogicFolding, this metric jumped to 238 MTr/mm² in a single generation. Simultaneously, the energy efficiency of the performance cores improved by approximately 41%, and the maximum operating frequency increased by approximately 13%.
Huawei’s Kirin 2026 will achieve a clock frequency of 3.1 GHz. (Source: Huawei)
“This set of data shows that, without relying on process node evolution, performance gains close to or even exceeding those of traditional scaling can still be achieved through structural reconfiguration and path compression. This also constitutes the first system-level verification of τ scaling in a real-world product,” He shared.
At a higher level, CircuitFolding and ChipFolding further extend optimization to clock networks and system architecture, reducing latency through cross-layer path convergence.
“When we elevate our perspective from a single chip to the entire AI system, communication time becomes extremely critical,” He pointed out, noting that over 80% of system energy consumption comes from data transport, and over 70% of costs come from data storage.
To reduce system latency (τ), Huawei designed the Unified Bus (UB), which reduces latency from microseconds to approximately 100 nanoseconds (about a 500-fold reduction) through memory semantic communication. In traditional architectures, data cross-node communication requires multiple protocol conversions, resulting in complex paths, high latency, and high costs. UB, through a fully peer-to-peer architecture, directly avoids these cross-protocol conversions, allowing data to be transmitted at the memory semantic level. This significantly reduces latency, improves reliability, and simplifies the entire system. The ultimate goal is to make large-scale AI systems as close as possible to “System as one chip”—operating like a single chip.
However, in terms of interconnect implementation, the challenge becomes: As single-chip bandwidth increases from hundreds of Gbps to Tbps, traditional electrical interconnects begin to reach their limits. Transmission distances shorten, cables become too large, and even the power supply and heat dissipation become strained. To address this challenge, Huawei introduced the Hi-ONE optical interconnect engine. A single module can provide 8 Tb/s bandwidth, consistent with the UB bandwidth. Meanwhile, the electrical interconnect distance is compressed to about 5 centimeters, while the overall system connection distance can be extended to the 100-meter level. This allows computing power to be distributed across racks instead of being concentrated in a single rack, thus better controlling power density and heat dissipation pressure, and making high-density interconnection in hyperscale data centers practically feasible for the first time.
Huawei’s SystemFolding approach aims to redistribute memory, I/O, and power, which were originally concentrated at the chip edge, from the two-dimensional boundary to the “surface” of three-dimensional space. This allows these critical resources to expand synchronously on an area scale, just like computing power, thereby alleviating expansion imbalances.
According to Huawei’s plan, the SystemFolding architecture will become the dominant direction in the future. It predicts that by 2035, system integration will increase by more than 100×. In terms of technology, chiplets and 2.5D packaging will remain the mainstay before 2030, after which a gradual shift will occur toward a three-dimensional system architecture that fully incorporates Folding.
τ law scaling roadmap
τ scaling roadmap (Source: Huawei)
When discussing the future roadmap, He further summarized the phased achievements of τ scaling over the past six years and gave a clear direction for its evolution. She stated, “At the circuit level, transistor density has increased from 155 MTr/mm² to 240–300, and is rapidly approaching and even exceeding 400; considering system design, effective transistor density has also increased from less than 100 to over 250, indicating that the ‘non-node scaling path’ based on τ optimization is sustainable. Simultaneously, this path opens up new space for SoC performance release, with CPU large core frequencies expected to break 5 GHz before 2031 (as shown in the figure above).”
“τ scaling” vs. “process-chip paradigm”
From an industry perspective, Huawei’s proposed τ scaling path is not a continuation of existing routes, but rather a deviation from the current logic of semiconductor development. Compared to the technological directions represented by companies such as Intel, TSMC, and Nvidia, its difference mainly lies in the definition of the “source of performance.”
Currently, other paths still revolve around the combination of “advanced process technology + architecture”:
TSMC/Samsung represent a “process-driven” model, advancing 3-nm and 2-nm nodes through EUV to continuously provide a foundation for higher transistor density and energy efficiency.
Intel, while advancing “advanced process technology + packaging (Intel 4/3 + Foveros/EMIB),” still relies on node leadership as its core competitiveness.
Nvidia, on the other hand, follows a typical “architecture-driven + software ecosystem” path, amplifying performance on advanced nodes through GPU parallel architecture and the CUDA software system.
These paths share the common premise that performance improvements ultimately depend on the fundamental conditions provided by advanced process technology. In contrast, Huawei adopts a different assumption in τ scaling: In the event that advanced process technology is unsustainable or unavailable, it achieves approximate benefits through system-level engineering methods.
Challenges and prospects
When discussing the future evolution of this technological path, He also clearly pointed out that it still faces multiple challenges.
First, there are shortcomings in design methodologies and toolchains. Traditional toolchains and methodologies cannot fully support free logic design, necessitating the construction of a completely new design system around folding and continuous iterative optimization in practice.
Second, there are pressures related to energy efficiency and thermal management. As chip power consumption continues to rise, thermal issues have crossed 12 orders of magnitude from milliwatts to gigawatts, from devices and circuits to systems, placing higher demands on engineering implementation.
To address this, it is necessary not only to introduce high-density capacitors inside the chip to cope with transient current surges, but also to systematically optimize thermal resistance and heat dissipation paths at the packaging and system levels. These challenges mean that τ scaling is not a single technical problem, but a systems engineering problem that permeates the entire stack.
Despite the obvious challenges, He still gives a fairly clear assessment of the prospects of this technical path. She stated that after six years of practice, “the τ scaling path has proven to be feasible, universal, and sustainable.” From a specific evolutionary perspective, at the circuit level, transistor density has increased from 155 MTr/mm² to 240–300 and is approaching 400 or more. In terms of performance, CPU core frequency is expected to break through 5 GHz before 2031. Meanwhile, with the combined effects of logic folding and hardware/software co-optimization, Kirin SoC energy efficiency is expected to continue to improve significantly over the next three to five years. On the system side, its AI computing platform will also continue to expand along the same path, providing lower latency and higher-scale computing capabilities.
In summary, He emphasized that the significance of this path is not limited to technological breakthroughs themselves, but lies in providing a new evolutionary logic—using time as a unified goal, continuously driving the evolution of semiconductor system performance without completely relying on advanced processes.