CMOS pushes towards 100Mops/mW – 10/8/2012 – Electronics Weekly

Dutch lab Holst Centre is working towards 100Mops/mW processing as it plans for the ‘Internet of things’. By 2020, estimates the lab, 50 billion objects will be connected to the internet, many of them machine-to-machine or mobile where low power…

Dutch lab Holst Centre is working towards 100Mops/mW processing as it plans for the ‘Internet of things’.

By 2020, estimates the lab, 50 billion objects will be connected to the internet, many of them machine-to-machine or mobile where low power consumption is key.
“Power consumption is proportional to CxfxVdd2, so the easy solution is to reduce Vdd [supply voltage] and hence reduce your power consumption,” said Harmke de Groot, programme director for ultra-low power wireless and DSP at Holst Centre

However, as Vdd gets near to 0.4V, several problems emerge which frustrate power improvements.
One is the failure of power gating.
Fine grain power gating – turning off as much unused logic as possible – is a valuable power saving technique but at Vdd=0.4V p-mosfet switches that worked perfectly at 1.1V now drop 0.2V when ‘on’- halving the supply and dramatically slowing subsequent logic.
Holst’s answer is to make a separate connection to the ‘body’ of the mosfet. For supply voltages above 0.6V, the body is connected to the Vdd rail, as it is in a standard rail switch.

When it is required to pass current for Vdd<0.6V, a control circuit connects its body to 0V, restoring its low on-resistance and passing on the full rail voltage.
“On low voltage [<0.6V], swapped bias on-enabled switches double the maximum clock frequency without increasing the energy costs,” said de Groot. “It enabled us to fulfil our target of 1MHz 88µW operation at 0.4V.”
The body cannot be connected permanently to 0V, as off-leakage would climb at higher Vdd.
Because it requires sub-threshold operation, circuit speed drops rapidly as Vdd is reduced, leaving functional blocks vulnerable to being just-too-slow through process variation across a wafer.
This has been tacked in two ways.
The first one has been to purge the design library of blocks that are particularly vulnerable to process variations, which has tended to be the more complex blocks, said de Groot.
The second is to insert ‘canary flip-flops’ in parallel with functional blocks along critical timing paths.
These canary flip-flops are designed to be slightly slower than the critical logic they run alongside and, like canaries in a coal mine, give early warning of trouble – timing trouble in this case – allowing Vdd to be incrementally increased to speed processing and insure the critical path always executes properly.
Vdd is set by an on-chip buck converter using an off-chip inductor.
Fabricated in 40nm LP (low-power) CMOS, processing power of a test chip could be throttled over almost 9x by varying Vdd from 0.4 to 1.1V, while specific consumption varied from 2 to 5µW/Mops.
The chip was demonstrated running from a lemon.
Holst Centre is a joint venture between Belgian lab IMEC and Dutch research organisation TNO.

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