Build a RISC-V CPU From Scratch

It’s a certain kind of itch that drives people to voluntarily build their own CPU. We start thinking about the papered-over gap in our understanding, the one that lurks between how logic gates and flip-flops work individually and how machine…

It’s a certain kind of itch that drives people to voluntarily build their own CPU. We start thinking about the papered-over gap in our understanding, the one that lurks between how logic gates and flip-flops work individually and how machine code controls a fully assembled processor. What exactly happens in the magic zone where hardwired circuits start dancing to software’s ever-changing tune?

It turns out this itch afflicts enough people that there are commercial kits for makers who want to put a CPU together to see (or hear) it tick, and the Web is littered with home-brewed 4-bit and 8-bit CPUs with architectures that would be familiar to an engineer from the 1970s. I should know—I made one myself. But then I began to wonder: Could I build my own CPU featuring some of the latest technology? Could I design my own fully compliant 32-bit RISC-V central processing unit?

RISC-V is an open-source architecture that’s about 11 years old, and is now starting to make inroads in a world dominated by the x86 and ARM CPU architectures. I was alerted to the possibilities of RISC-V by the work of Robert Baruch, who started a similar project about two years ago but hasn’t yet completed his processor, in part because he had to keep redesigning components he’d built early on to meet the needs of an evolving design.

Illustraton of PCBs
James Provost
The modular nature of the RISC-V design let me build the Pineapple One as a stack of individually testable 10-by-10-centimeter PCBs with different functions [clockwise, from top left]: VGA driver; RAM; transport layer; shifter; ALU; register file; control unit; program counter; ROM.
Instead, I started out by building my complete design—which I dubbed Pineapple One—in Logisim Evolution, a logic-circuit simulator. After consulting the official RISC-V manual and the first edition of David Patterson and John Hennessy’s book Computer Organization and Design, RISC-V Edition (Elsevier, 2017), and pushing Logisim to its outer limits, I had a working simulation of Pineapple One that met the requirements of a basic RISC-V CPU in six months.

In implementing the RISC-V architecture, I was amazed at how much more sense the architecture made compared to the conventional complex instruction set I’d used in my earlier home-brew CPU. Redundancies had been eliminated, and the processor’s registers—the scratchpads that store the CPU’s working memory—were more flexible. Another big advantage was that RISC-V is a well-documented modular design, so I knew just what each block had to do. My goal was to design each block in my own way, but make sure it performed in compliance with the RISC-V standards. (This dictated that my CPU be 32-bit, as RISC-V instructions are at least that long by definition.)

Physically, the Pineapple One is distributed over a vertical stack of eight square printed circuit boards that are about 10 centimeters on a side, plus a card that handles a VGA display interface. It uses over 230 integrated circuits, mostly from the 74HCT series of logic chips. My biggest challenge was implementing a barrel shifter—a circuit that can shift around the bits in a register by a controllable amount. I first tried a fast implementation that would require over 80 components, but try as I might, I couldn’t get it to fit onto my PCBs. So instead I went with a low-component approach that essentially suspends the operation of the rest of the CPU until my shifter finishes cranking away. Due to the Pineapple One’s long traces, as compared to a single-chip CPU, I also struggled to manage parasitic capacitance and impedance, which meant debugging some really strange behaviors.

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James Provost
While there are provisions for instructions that can range in length between 16 bits and a theoretically unlimited number, here are the fixed 32-bit formats of the four core types of RISC-V instructions. Some instructions combine an opcode with additional functional fields to define behavior, while others allow multiple source registers to be combined with so-called immediate data, with the results placed in the destination register.
I tested each individual board by using an Arduino microcontroller to simulate inputs from the rest of the computer, and to monitor outputs for correctness. I 3D-printed a nice case to hold the entire stack of PCBs and input/output connectors, so that it’s possible to hook up a keyboard and VGA display directly to the Pineapple One. There are four general-purpose I/O ports—two 8-bit inputs and two outputs.

My friend Jan Vykydal helped me set up a RISC-V-compliant compiler to work properly, so I wrote some system software and demo programs in C. The compiler produces machine code, and I use a Python script that takes the code and flashes it to the CPU’s memory. Even though Pineapple One runs at only 500 kilohertz, that’s still fast enough to play a simple computer game like Snake in real time, and the 512 kilobytes of program memory and 512 kB of RAM are ample.

Ultimately, I would like to upgrade the processor a little bit so it can run more-complex programs. I’d also like to add more expansion boards, such as a sound card. You can find schematics and a bill of materials on Hackaday, but ultimately it would be great to offer it as a kit to others interested in understanding contemporary CPU design.

This article appears in the June 2021 print issue as “Build Your Own RISC-V CPU.”